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Post by Andreas Schilling 🇺🇦 on X

Andreas Schilling 🇺🇦@aschilling

Lots of talking about the µarchitectures with Lunar Lake. But it’s also interesting how Intel achieved to be 99% process-agnostic with Lion Cove. The P-core database was not build in thousands of functional blocks, but rather using fewer and bigger cells.

164 likes7 repliesPosted Jun 4, 2024

View the original on X Written by Andreas Schilling 🇺🇦. Captured Sep 4, 2026.

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Based on absolute engagement — the platform doesn’t expose follower counts here, so large accounts score higher.

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Why it worked

Short enough to read in full without expanding, which removes a step before the point lands.
Short sentences keep the pace up, so the reader never has to re-read a line.

The mechanics

Hook: Plain observation
Structure: Hook → Landing
Style: Conversational paragraphs at a steady pace.
Tone: plain, matter-of-fact
Written for: Engineers and technical teams

Analysis by ViralLoop — not written by the original author.

Topics

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Anthropic just pulled Claude Code from the Pro plan. Pro users wanting it need Max now. $100/month minimum. 5x jump. I'm on Max 20x so I'm fine. Flagging for anyone on Pro who's about to find out. No announcement. Just a pricing page edit.

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I think @bot is another “Claude Code” moment for AI. I would estimate my personal AI usage is up something like 100x. And for everyone who reached out about how to build a “podcast summarizer” it took me about 15 seconds in Grok Bot and is better than what I had before.

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More from Andreas Schilling 🇺🇦

Andreas Schilling 🇺🇦

.@Intel just announced Crescent Island. Crescent Island is a new Intel Data Center GPU offering that will arrive in the second half of 2026. Knows features: - air-cooled - Xe3P microarchitecture - 160 GB of LPDDR5X Looks like a competitor to Rubin CPX and token optimized XPUs.

Andreas Schilling 🇺🇦

Qualcomm lifted the architectural details on the Oryon SoC aka @Snapdragon X Elite today. The chip is composed of three quad-core-cluster with 12 MB of L2$ per cluster and an additional 6 MB SLC. - latency to SLC: 26-29 ns - latency to DRAM: 102-104 ns t.co

Andreas Schilling 🇺🇦

This was the best I could do given the conditions in the room. That’s #EPYC #Turin with Zen 5 CCDs. It’s 16 CCDs with 8 Zen 5 cores each. I did a mistake in my previous Tweet. Thanks for pointing me to this.

Andreas Schilling 🇺🇦 on Engineering · ViralLoop