Andreas Schilling 🇺🇦 on Engineering

Andreas Schilling 🇺🇦@aschilling

Qualcomm lifted the architectural details on the Oryon SoC aka @Snapdragon X Elite today. The chip is composed of three quad-core-cluster with 12 MB of L2$ per cluster and an additional 6 MB SLC. - latency to SLC: 26-29 ns - latency to DRAM: 102-104 ns t.co

152 likes9 repliesPosted Jun 13, 2024

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Viral score

Based on absolute engagement — the platform doesn’t expose follower counts here, so large accounts score higher.

From likes, comments.

Why it worked

Opens with a short, self-contained line that is easy to take in at a glance.
Uses short lines and white space, which makes a long post feel quick to read.
Follows a clear Hook → Context → List → Landing shape, so the reader always knows where they are.
Ends on a short line that is easy to quote and repeat.
Short enough to read in full without expanding, which removes a step before the point lands.
Short sentences keep the pace up, so the reader never has to re-read a line.

The mechanics

Hook: Plain observation
Structure: Hook → Context → List → Landing
Style: Short lines with heavy white space, built to be scanned.
Tone: punchy
Written for: Engineers and technical teams

Analysis by ViralLoop — not written by the original author.

Topics

Engineering

Post by Andreas Schilling 🇺🇦 on X